1. Field of the Invention
The embodiments herein generally relate to a fabrication process for forming a hardmask for use in a lithographic multi-patterning fabrication process.
2. Description of the Background Art
Reliably producing submicron and smaller features is one of the key requirements of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, with the continued miniaturization of circuit technology, the dimensions of the size and pitch of circuit features, such as interconnects, have placed additional demands on processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise imaging and placement of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is critical to further increases in device and interconnect density. Additionally, forming sub-micron size features and interconnects with reduced waste of intermediate materials, such as resists and hardmask materials, is desired.
As circuit densities increase for next generation devices, the width or pitch of interconnects, such as vias, trenches, contacts, devices, gates and other features, as well as the dielectric materials there between, are decreasing to 45 nm and 32 nm dimensions, As device scaling was extended to further below the resolution limit of the lithography scanners, multi-patterning was employed to enable meeting the feature density requirements of today's integrated devices. Multi-patterning is a process of performing several resist coating, lithographic patterning, and etching operations to ultimately pattern a film layer in multiple steps. When combined, the overlapping pattern operations form the features in an underlying hardmask layer, which when fully patterned, may be used to pattern an underlying layer, or serve as an implant or diffusion mask.
During simple, non-multi-patterning of an underlying hardmask layer, the current “ultra violet light” wavelengths used for exposure will reflect off the un-patterned interface of the resist and conventional hardmask layer, and may also reflect off the underlying previously formed features, and will as a result, affect the precision of the sidewalls and size of the exposed and developed features in the resist. To correct for this, optical proximity correction (OPC) may be employed in the lithograph mask, which results in an intentional distortion of the position where the resist exposing wavelength reaches the resist, with the result that actually formed developed feature meets a desired feature size and profile. However, with smaller geometries and reflection of the provided exposure's ultra violet electromagnetic energy, OPC is unable to cure distortion effects without additional processing.
One enabler of multiple patterning has been the use of optically opaque films to block the exposure wavelength from penetrating to the previously masked hardmask layer, which is sometimes called a memory or memorization, layer. The function of the memory layer is to serve as the hardmask for etching a pattern into a layer there below which may, for example, be a dielectric material, or may, for example, be a mask for another purpose. To pattern the memory layer multiple times, a tri-layer scheme, having an uppermost resist layer, is used in each pattern step. The tri-layer has sufficient opacity to prevent the lithographic resist exposure wavelength from reaching the surface of the memory layer and thus preventing reflections of the exposure electromagnetic energy off of previously formed hardmask features back into the resist, which would result in unintended exposure of areas therein. After each patterning step of the multi-patterning scheme, the tri-layer must be stripped off with wet and/or gas based chemistries, and the wafer and the memory layer must be wet cleaned and dried and a new tri-layer applied thereto before the next pattern of the multi-pattern can be formed in the memory layer.
While the benefits of multiple patterning in terms of resolution, depth of focus and lithographic defect sensitivity are understood, there is additional desire to control the process budget and increase and maintain yield.
Therefore, there is a need for an improved method for lithographically creating a multi-patterned hardmask on a substrate.